P89LPC9331_11 Datasheet, PDF (49/94 Pages) NXP Semiconductors – 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable

NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.25 SPI
The P89LPC9331/9341/9351/9361 provides another high-speed serial communication
interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication
bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be
supported in either Master mode or Slave mode. It has a Transfer Completion Flag and
Write Collision Flag Protection.
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
SPI clock (master)
SPI CONTROL
MSTR
SPEN
8-BIT SHIFT REGISTER
READ DATA BUFFER
clock
CLOCK LOGIC
S
M
M
S
PIN
CONTROL
LOGIC
S
M
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SPI STATUS REGISTER
SPI
interrupt
request
Fig 16. SPI block diagram
SPI CONTROL REGISTER
internal
data
bus
002aaa900
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
• SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
Typical connections are shown in Figure 17 through Figure 19.
P89LPC9331_9341_9351_9361
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 January 2011
© NXP B.V. 2011. All rights reserved.
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