LPC11C24FBD48301 Datasheet, PDF(47/62 Page) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C

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LPC11C24FBD48301 Datasheet, PDF (47/62 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN

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NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 ïs and 0.9 ïs for Standard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

70 %

SDA 30 %

SCL

70 %

30 %

tSU;DAT

70 %

30 %

tHD;DAT

70 %

30 %

1 / fSCL

70 %

30 %

tLOW

tHIGH

tVD;DAT

70 %

30 %

Fig 20. I2C-bus pins clock timing

002aaf425

10.6 SPI interfaces

Table 18. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter

Conditions

Min

SPI master (in SPI mode)

Tcy(clk)

clock cycle time

full-duplex mode

[1]

when only transmitting [1] 40

tDS

data set-up time

in SPI mode

[2]

2.4 V ï£ VDD ï£ 3.6 V

2.0 V ï£ VDD < 2.4 V [2] 20

1.8 V ï£ VDD < 2.0 V [2] 24

tDH

data hold time

in SPI mode

[2]

tv(Q)

data output valid time in SPI mode

[2]

th(Q)

data output hold time in SPI mode

[2]

SPI slave (in SPI mode)

Tcy(PCLK) PCLK cycle time

Typ Max

LPC11CX2_CX4

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3.1 â 15 May 2013

Unit

47 of 62

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