ISP1582 Datasheet, PDF (44/69 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
Reset
0
0
0
0
0
0
0
0
Bus reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8.4.7 DMA Endpoint register (address: 58h)
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in Table 57.
Table 57. DMA Endpoint register: bit allocation
Bit
7
6
5
4
Symbol
reserved
Reset
-
-
-
-
Bus reset
-
-
-
-
Access
-
-
-
-
3
2
1
EPIDX[2:0]
0
0
0
0
0
0
R/W
R/W
R/W
0
DMADIR
0
0
R/W
Table 58.
Bit
7 to 4
3 to 1
0
DMA Endpoint register: bit description
Symbol
Description
-
reserved
EPIDX[2:0]
Endpoint Index: Selects the indicated endpoint for DMA access
DMADIR
DMA Direction:
0 — Selects the RX/OUT FIFO for DMA read transfers
1 — Selects the TX/IN FIFO for DMA write transfers
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (2Ch) at any time. Doing so will result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not
reference the same endpoint on the Endpoint Index register.
8.4.8 DMA Burst Counter register (address: 64h)
Table 59 shows the bit allocation of the 2-byte register.
Table 59. DMA Burst Counter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BURSTCOUNTER[12:8]
Reset
-
-
-
0
0
0
0
0
Bus reset
-
-
-
0
0
0
0
0
Access
-
-
-
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
BURSTCOUNTER[7:0]
Reset
0
0
0
0
0
0
1
0
Bus reset
0
0
0
0
0
0
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISP1582_7
Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
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