P89CV51RB2 Datasheet, PDF (43/73 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals

NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
toggle when there is a match between the PCA counter and the module’s
capture/compare register.
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to
be set when there is a match between the PCA counter and the module’s
capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode,
these registers are used to control the duty cycle of the output.
PCA TIMER/COUNTER
CF CR
CCON
-
CCF4 CCF3 CCF2 CCF1 CCF0 _(D8H)
MODULE0
MODULE1
MODULE2
MODULE3
MODULE4
IE.6
IE.7
EC
EA
to
interrupt
priority
decoder
CMOD.0 ECF
Fig 20. PCA interrupt system
CCAPMn.0
ECCFn
002aaa533
Table 32. CMOD - PCA counter mode register (address C1H) bit allocation
Not bit addressable; reset value: 00H.
Bit
7
6
5
4
3
2
1
Symbol CIDL WDTE
-
-
-
CPS1 CPS0
0
ECF
P89CV51RB2_RC2_RD2_1
Product data sheet
Rev. 01 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
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