LPC2420 Datasheet, PDF (42/73 Pages) NXP Semiconductors – Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface

NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
7.24.4.4 Power domains
The LPC2420/2460 provides two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the Battery
RAM.
On the LPC2420/2460, I/O pads are powered by the 3.3 V (V_DD(3V3)) pins, while the
V_{DD(DCDC)(3V3)} pins power the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
V_DD(3V3) and V_{DD(DCDC)(3V3)} pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V_DD(3V3)) and
a dedicated 3.3 V supply for the CPU (V_{DD(DCDC)(3V3)}). Having the on-chip DC-DC
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
7.25 System control
7.25.1 Reset
Reset has four sources on the LPC2420/2460: the RESET pin, the Watchdog reset,
power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the Wake-up timer (see description in Section 7.24.3 “Wake-up
timer”), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, and a fixed number of clocks have passed.
Once the internal reset is removed, all of the processor and peripheral registers have
been initialized to predetermined values and the LPC2420/2460 continues with booting
from an external static memory.
7.25.2 Boot process
The processor always boots from the off-chip static memory bank 1, executing code from
address 0x8100 0000 (see Table 5 “LPC2420/2460 memory usage and details”). During
the boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled,
and the external memory banks 0 and 1 are configured with the same data bus width. The
data bus width is determined by the setting of the two boot pins. Unused address pins are
configured as GPIO. See Section 11.2 “Suggested boot memory interface solutions” for
an example of address and data bus interfacing.
LPC2420_60_3
Preliminary data sheet
Rev. 03 — 20 November 2008
© NXP B.V. 2008. All rights reserved.
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