PCF2129A Datasheet, PDF (40/68 Pages) NXP Semiconductors – Integrated RTC, TCXO and quartz crystal

NXP Semiconductors
PCF2129A
Integrated RTC, TCXO and quartz crystal
The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot
be cleared by using the interface. Instructions for clearing it can be found in
Section 8.10.5.
8.12.4 Alarm interrupts
Generation of interrupts from the alarm function is controlled via the bit AIE (register
Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register
Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for
alarm interrupts.
minute counter 44 45
minute alarm 45
AF
INT
SCL
instruction
8th clock
CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 23. AF timing diagram
8.12.5 Timestamp interrupts
Interrupt generation from the timestamp function is controlled using the TSIE bit (register
Control_2). If TSIE is enabled the INT pin follows the status of the flags TSFx. Clearing
the flags TSFx immediately clears INT. No pulse generation is possible for timestamp
interrupts.
8.12.6 Battery switch-over interrupts
Generation of interrupts from the battery switch-over is controlled via the BIE bit (register
Control_3). If BIE is enabled, the INT pin follows the status of bit BF (register Control_3).
Clearing BF immediately clears INT. No pulse generation is possible for battery
switch-over interrupts.
8.12.7 Battery low detection interrupts
Generation of interrupts from the battery low detection is controlled via the BLIE bit
(register Control_3). If BLIE is enabled the INT pin will follow the status of bit BLF (register
Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when
bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared via
the interface.
PCF2129A_1
Product data sheet
Rev. 01 — 13 January 2010
© NXP B.V. 2010. All rights reserved.
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