SSTUM32866 Datasheet, PDF (4/28 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications

NXP Semiconductors
SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
RESET
CK
CK
D2, D3, D5, D6, ₁₁
D8 to D14
VREF
C1
PAR_IN
LPS0
(internal node)
CE
D
CLK
R
D2, D3, D5, D6,
D8 to D14 ¹¹
PARITY
CHECK
0
D
1
CLK
R
D2, D3, D5, D6,
11 D8 to D14
Q2A, Q3A,
11 Q5A, Q6A,
Q8A to Q14A
11 _{Q2B, Q3B,}
Q5B, Q6B,
Q8B to Q14B
D
CLK
R
CE
1
D
0
CLK
R
PPO
QERR
C0
CLK
2-BIT
COUNTER
R
LPS1
(internal node)
0
D
1
CLK
R
002aaa650
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
SSTUM32866_1
Product data sheet
Rev. 01 — 29 June 2007
© NXP B.V. 2007. All rights reserved.
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