ES-LPC407X-8X Datasheet, PDF (4/6 Pages) NXP Semiconductors – Errata sheet LPC407x/8x

NXP Semiconductors
ES_LPC407x/8x
Errata sheet LPC407x/8x
3. Functional problems detail
n/a
4. AC/DC deviations detail
n/a
5. Errata notes
5.1 Note.1
The General Purpose I/O (GPIO) pins have configurable pull-up/pull-down resistors where
the pins are pulled up to the V_DD level by default. During power-up, an unexpected glitch
(low pulse) could occur on the port pins as the V_DD supply ramps up.
ES_LPC407X_8X
Errata sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 September 2012
© NXP B.V. 2012. All rights reserved.
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