DAC1001D125 Datasheet, PDF (4/25 Pages) NXP Semiconductors – Dual 10-bit DAC, up to 125 Msps

NXP Semiconductors
DAC1001D125
Dual 10-bit, up to 125 Msps DAC
Table 2. Pin description …continued
Symbol
Pin
Type^[1]
n.c.
14
DGND
15
G
V_DDD
16
S
WRTA/IQWRT
17
I
CLKA/IQCLK
18
I
CLKB/IQRESET 19
I
WRTB/IQSEL
20
I
DGND
21
G
V_DDD
DB9
22
S
23
I
DB8
24
I
DB7
25
I
DB6
26
I
DB5
27
I
DB4
28
I
DB3
29
I
DB2
30
I
DB1
31
I
DB0
32
I
n.c.
33
n.c.
34
n.c.
35
n.c.
36
PWD
37
I
AGND
38
S
IOUTBP
39
O
IOUTBN
40
O
BVIRES
41
I
GAINCTRL
42
I
REFIO
43
I/O
AVIRES
44
I
IOUTAN
45
O
IOUTAP
46
O
V_DDA
MODE
47
S
48
I
Description
not connected
digital ground
digital supply voltage
input write port A/input write IQ in Interleaved mode
input clock port A/input clock IQ in Interleaved mode
input clock port B/reset IQ in Interleaved mode
input write port B/select IQ in Interleaved mode
digital ground
digital supply voltage
DAC B, data input bit 9 (MSB)
DAC B, data input bit 8
DAC B, data input bit 7
DAC B, data input bit 6
DAC B, data input bit 5
DAC B, data input bit 4
DAC B, data input bit 3
DAC B, data input bit 2
DAC B, data input bit 1
DAC B, data input bit 0 (LSB)
not connected
not connected
not connected
not connected
power-down mode
analog ground
DAC B current output
complementary DAC B current output
adjust DAC B for full-scale output current
gain control mode
reference I/O
adjust DAC A for full-scale output current
complementary DAC A current output
DAC A current output
analog supply voltage
select between Dual-port or Interleaved mode
[1] Type description: S = Supply; G = Ground; I = Input; O = Output; I/O = Input/Output.
DAC1001D125_1
Product data sheet
Rev. 01 — 24 November 2008
© NXP B.V. 2008. All rights reserved.
4 of 25