ADC1415S Datasheet, PDF (4/39 Pages) NXP Semiconductors – Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1415S series
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
terminal 1
index area
REFB 1
REFT 2
AGND 3
VCM 4
VDDA5V 5
AGND 6
INM 7
INP 8
AGND 9
VDDA3V 10
ADC1415S
HVQFN40
30 D0
29 D1
28 D2
27 D3
26 D4
25 D5
24 D6
23 D7
22 D8
21 D9
terminal 1
index area
REFB 1
REFT 2
AGND 3
VCM 4
VDDA5V 5
AGND 6
INM 7
INP 8
AGND 9
VDDA3V 10
ADC1215S
HVQFN40
30 D0_D1_P
29 D0_D1_M
28 D2_D3_P
27 D2_D3_M
26 D4_D5_P
25 D4_D5_M
24 D6_D7_P
23 D6_D7_M
22 D8_D9_P
21 D8_D9_M
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Transparent top view
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Fig 2. Pin configuration with CMOS digital outputs
selected
Transparent top view
Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
VDDA5V
AGND
INM
INP
AGND
VDDA3V
VDDA3V
CLKP
CLKM
DEC
OE
PWD
Pin description (CMOS digital outputs)
Pin
Type ^[1]
Description
1
O
bottom reference
2
O
top reference
3
G
analog ground
4
O
common-mode output voltage
5
P
5 V analog power supply
6
G
analog ground
7
I
complementary analog input
8
I
analog input
9
G
analog ground
10
P
3 V analog power supply
11
P
3 V analog power supply
12
I
clock input
13
I
complementary clock input
14
O
regulator decoupling node
15
I
output enable, active LOW
16
I
power down, active HIGH
ADC1415S_SER_3
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
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