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74LVT245B Datasheet, PDF (4/15 Pages) NXP Semiconductors – 3.3V Octal transceiver with direction pin (3-State)
NXP Semiconductors
74LVT245B
3.3 V octal transceiver with direction pin (3-state)
6. Functional description
Table 3.
Inputs
OE
L
L
H
Function selection
DIR
L
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
7. Limiting values
Inputs/outputs
An
An = Bn
inputs
Z
Bn
inputs
Bn = An
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1][2]
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+4.6
V
VI
input voltage
[3] −0.5
+7.0
V
VO
output voltage
output in OFF or HIGH state
[3] −0.5
+7.0
V
IIK
input clamping current
VI < 0
−50
-
mA
IOK
output clamping current
VO < 0
−50
-
mA
IO
output current
output in LOW state
output in HIGH state
-
128
mA
−64
-
mA
Tstg
storage temperature
Tj
junction temperature
Ptot
total power dissipation
Tamb = −40 °C to +85 °C
−65
+150
°C
[2] -
150
°C
[4] -
500
mW
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
[3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[4] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
74LVT245B_2
Product data sheet
Rev. 02 — 8 May 2008
© NXP B.V. 2008. All rights reserved.
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