LPC2921_10 Datasheet, PDF (37/84 Pages) NXP Semiconductors – ARM9 microcontroller with CAN, LIN, and USB

NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
• Motor controller: The PWM provides multi-phase outputs, and these outputs can be
controlled to have a certain pattern sequence. In this way the force/torque of the
motor can be adjusted as desired. This makes the PWM function as a motor drive.
APB system bus
IRQ pwm
IRQ capt_match
PWM
CONTROL
&
REGISTERS
APB DOMAIN
update
capture data
PWM counter value
config data
IRQs
sync_in
transfer_enable_in
PWM DOMAIN
PWM,
COUNTER,
PRESCALE
COUNTER
&
SHADOW
REGISTERS
match outputs
capture inputs
trap input
carrier inputs
Fig 7. PWM block diagram
transfer_enable_out
sync_out
002aad837
The PWM block diagram in Figure 7 shows the basic architecture of each PWM. PWM
functionality is split into two major parts, a APB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the APB domain.
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling Control SubSystem (MSCSS), each PWM has
its individual clock source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale
and the timer counters within each PWM run on this clock CLK_MSCSS_PWMx, and all
time references are related to the period of this clock. See Section 6.15 for information on
generation of these clocks.
6.14.5.2 Synchronizing the PWM counters
A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
See Figure 5 for details of the connections of the PWM modules within the MSCSS in the
LPC2921/2923/2925. PWM0 can be master over PWM1; PWM1 can be master over
PWM2, etc.
LPC2921_23_25_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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