LH7A400 Datasheet, PDF (36/65 Pages) Sharp Electrionic Components – 32-Bit System-on-Chip

LH7A400
NXP Semiconductors
32-Bit System-on-Chip
SMC Waveforms
Figure 10 and Figure 11 show the waveform and
timing for an External Asynchronous Memory Write.
Note that the deassertion of nWE can precede the
deassertion of nCS by a maximum of one HCLK, or at
minimum, can coincide (see Table 12). Figure 12 and
Figure 13 show the waveform and timing for an Exter-
nal Asynchronous Memory Read.
0
1
2
3
4
HCLK
tWC
A[27:0]
VALID ADDRESS
tDVWE,
tDVBE
tDHWE,
tDHBE
D[31:0]
tAVCS
VALID DATA
tCS
tAHCS
nCSx
tAVWE
nCS Valid
tWE
tCSHWE
nWE
tAVBE
nWE Valid
tBEW
WRITE EDGE
tCSHBE
nBLE
nBLE Valid
LH7A400-201
Figure 10. External Asynchronous Memory Write with 0 Wait States (BCRx:WST1 = 0b000)
36
Rev. 01 — 16 July 2007
Preliminary data sheet