PCF8532_11 Datasheet, PDF (35/49 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

NXP Semiconductors
PCF8532
Universal LCD driver for low multiplex rates
12. Application information
12.1 Cascaded operation
In large display configurations, up to 8 PCF8532 can be distinguished on the same
I²C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable
I²C-bus slave address (SA0). When cascaded PCF8532 are synchronized, they can
share the backplane signals from one of the devices in the cascade. Such an
arrangement is cost-effective in large LCD applications since the backplane outputs of
only one device need to be through-plated to the backplane electrodes of the display. The
other PCF8532 of the cascade contribute additional segment outputs but their backplane
outputs are left open-circuit (see Figure 23).
For display sizes that are not multiple of 640 elements, a mixed cascaded system can be
considered containing only devices like PCF8532 and PCF8533. Depending on the
application, one must take care of the software commands compatibility and pin
connection compatibility.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8532. This synchronization is guaranteed after the power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a multiplex mode when PCF8532
with different SA0 levels are cascaded). SYNC is organized as an input/output pin; the
output selection being realized as an open-drain driver with an internal pull-up resistor. A
PCF8532 asserts the SYNC line at the onset of its last active backplane signal and
monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it
will be restored by the first PCF8532 to assert SYNC. The timing relationship between the
backplane waveforms and the SYNC signal for the various drive modes of the PCF8532
are shown in Figure 25.
When using an external clock signal with high frequencies (f_clk(ext) > 4 kHz) it is
recommended to have an external pull-up resistor between pin SYNC and pin V_DD (see
Table 18). This resistor should be present even when no cascading configuration is used!
When using it in a cascaded configuration, care must be taken not to route the SYNC
signal to close to noisy signals.
The contact resistance between the SYNC pads of cascaded devices must be controlled.
If the resistance is too high, the device will not be able to synchronize properly. This is
particularly applicable to COG applications. Table 19 shows the limiting values for contact
resistance.
In the cascaded applications, the OSC pin of the PCF8532 with subaddress 0 is
connected to V_SS so that this device uses its internal clock to generate a clock signal at
the CLK pin. The other PCF8532 devices are having the OSC pin connected to V_DD,
meaning that this devices are ready to receive external clock, the signal being provided by
the device with subaddress 0.
In the case that the master is providing the clock signal to the slave devices, care must be
taken that the sending of display enable or disable will be received by both, the master
and the slaves at the same time. When the display is disabled the output from pin CLK is
disabled too. The disconnection of the clock may result in a DC component for the display.
PCF8532
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 February 2011
© NXP B.V. 2011. All rights reserved.
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