ADC1413D Datasheet, PDF (35/43 Pages) NXP Semiconductors – Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

NXP Semiconductors
ADC1413D series
ADC1413D series; serial JESD204A interface
Table 41. Cfg_7_CS_N (address 0826h)
Bit Symbol
Access
7
-
R
6
CS[0]
R/W
5 to 4 -
R
3 to 0 N[3:0]
R/W
Value
0
*
00
****
Description
not used
defines the number of control bits per sample, minus 1
not used
defines the converter resolution
Table 42. Cfg_8_Np (address 0827h)
Bit Symbol
Access
7 to 5 -
R
4 to 0 NP[4:0]
R/W
Value
000
*****
Description
not used
defines the total number of bits per sample, minus 1
Table 43. Cfg_9_S (address 0828h)
Bit Symbol
Access
7 to 1 -
R
0
S
R/W
Value
0000000
1
Description
not used
defines number of samples per converter per frame cycle
Table 44. Cfg_10_HD_CF (address 0829h)
Bit Symbol
Access Value
7
HD
R/W
*
6 to 2 -
R
00000
1 to 0 CF[1:0]
R/W
**
Description
defines high density format
not used
defines number of control words per frame clock cycle per link.
Table 45. Cfg01_2_LID (address 082Ch)
Bit Symbol
Access Value
7 to 5 -
R
000
4 to 0 LID[4:0]
R/W
11011
Description
not used
defines lane1 identification number
Table 46. Cfg02_2_LID (address 082Dh)
Bit Symbol
Access Value
7 to 5 -
R
000
4 to 0 LID[4:0]
R/W
11100
Description
not used
defines lane2 identification number
Table 47. Cfg02_13_fchk (address 084Ch)
Bit Symbol
Access Value
7 to 0 FCHK[7:0]
R
********
Description
defines the checksum value for lane1
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
ADC1413D_SER_4
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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