LH79524 Datasheet, PDF (34/64 Pages) NXP Semiconductors – System-on-Chip

LH79524/LH79525
NXP Semiconductors
System-on-Chip
External Memory Controller Waveforms
The External Memory Controller (EMC) handles
transactions with both static and dynamic memory.
STATIC MEMORY WAVEFORMS
This section illustrates static memory transaction
waveforms. Each wait state is one HCLK period.
nWAIT Input
The EMC’s Static Memory Controller supports an
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the begin-
ning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 11 through Figure 20.
Read and Write Waveforms
Figure 17 shows the Read cycle with zero wait
states. As shown in the figure, SWAITOENx and
SWAITRDx are programmed to 0 for minimum Read
cycle time.
The zero programmed into the SWAITRDx indicates
that the read occurs with zero wait states, on the first
rising edge following Address Valid. After a small prop-
agation delay, nOE is deasserted (as is nCSx), latching
the data into the SoC. The address line is held valid
one more HCLK period (‘C’ in the figure). Thus, the
minimum Read cycle is two HCLK periods.
Figure 18 shows the minimum write cycle time with
both SWAITWRx and SWAITWENx programmed to
zero. The write access time is determined by the number
of wait states programmed in the SWAITWRx register.
In Figure 18, nCSx is asserted coincident (following
a small propagation delay) with Valid Address. Data
becomes valid another small propagation delay later.
Unlike Read transactions, nWE (or nBLEx) assertion is
always delayed one HCLK cycle. The nBLEx signal has
the same timing as nWE for write to 8-bit devices that
use the byte lane enables instead of the write enables.
The nWE (or nBLEx) signal remains asserted for one
HCLK cycle when the nWE (or nBLEx) signal is deas-
serted and the data is latched into the external memory
device. Valid address is held for one additional cycle
before deassertion (‘C’ in the figure), as is the Chip
Select. The minimum Write cycle is three HCLK periods.
Read wait state programming uses the SWAITRDx
register. Figure 19 shows the results of programming
SWAITRDx to 0x3, setting the EMC for three wait
states. The deassertion of nOE is delayed from the first
rising HCLK edge following Valid Address, as in Figure
17, to the fourth rising edge, a delay of 3 HCLK periods.
Figure 20 shows the results of programming the
SWAITWRx and SWAITWENx registers for two Write
wait states: register SWAITWENx = 0x0, and SWAIT-
WRx = 0x2. Assertion of nCSx precedes nWE (nBLEx)
by one HCLK period. Then, instead of the nWE
(nBLEx) signal deasserting one HCLK period after
assertion, it is delayed two wait states and the signal
deasserts on the rising edge following two wait states.
Chapter 7 of the User’s Guide has detailed register
descriptions and additional programming examples.
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Rev. 01 — 16 July 2007
Preliminary data sheet