SC16C852SV Datasheet, PDF (33/48 Pages) NXP Semiconductors – 1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control. Table 27 shows transmission control
register bit settings; see Section 6.5.
Table 27. FLWCNTH register bits description
Bit
Symbol
Description
7:0
FLWCNTH[7:0] This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode.^[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control. Table 28 shows transmission control
register bit settings; see Section 6.5.
Table 28. FLWCNTL register bits description
Bit
Symbol
Description
7:0
FLWCNTL[7:0] This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode.^[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.19 Clock Prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 29. Clock Prescaler register description
Bit
Symbol
Description
7:4
CLKPRES[7:4] reserved
3:0
CLKPRES[3:0] clock prescaler value; reset to 0
SC16C852SV_1
Product data sheet
Rev. 01 — 23 September 2008
© NXP B.V. 2008. All rights reserved.
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