TFA9812 Datasheet, PDF (32/66 Pages) NXP Semiconductors – BTL stereo Class-D audio amplifier with I2S input

NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I²S input
Table 31.
Bit
15 to 8
7 to 0
Bit description of register 00h: miscellaneous I²C interpolator settings
Symbol
Description
VOL_L[15:8]
See Table 16 for suppression levels on left channel as
function of data byte setting.
VOL_R[7:0]
See Table 16 for suppression levels on right channel as
function of data byte setting.
9.5.3 Digital input format
Table 32.
Bit
Symbol
Default
Bit
Symbol
Default
Register address 02h: digital input format
15
14
13
RSD
RSD
RSD
0
0
0
7
6
5
RSD
RSD
RSD
0
0
0
12
RSD
0
4
RSD
0
11
RSD
0
3
DI_FOR2
0
10
RSD
0
2
DI_FOR1
1
9
RSD
0
1
DI_FOR0
1
8
RSD
0
0
WS_POL
0
Table 33.
Bit
3 to 1
0
Bit description of register 02h: digital input format
Symbol
Description
DI_FOR[2:0]
Digital audio input format:
0 = RSD
1 = RSD
2 = MSB-justified data up to 24 bits
3 = I²S data up to 24 bits
4 = LSB-justified 16-bit data
5 = LSB-justified 18-bit data
6 = LSB-justified 20-bit data
7 = LSB-justified 24-bit data
WS_POL
Enable WS signal polarity inversion:
0 = No WS signal polarity inversion
1 = WS signal polarity inversion enabled
9.5.4 Equalizer configuration
Table 34.
Bit
Symbol
Default
Bit
Symbol
Default
Register address 03h: equalizer configuration
15
14
13
12
RSD
RSD
RSD
RSD
0
0
0
0
7
6
5
4
RSD
RSD
RSD
RSD
0
0
0
0
11
RSD
0
3
RSD
0
10
RSD
0
2
RSD
0
9
RSD
0
1
EQ_BP
1
8
RSD
0
0
EQ_BND
0
TFA9812_1
Preliminary data sheet
Rev. 01 — 30 October 2008
© NXP B.V. 2008. All rights reserved.
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