PCF85176 Datasheet, PDF (32/43 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

NXP Semiconductors
PCF85176
Universal LCD driver for low multiplex rates
V_LCD
V_DD
R
≤
t_r
2C_b
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
V_DD V_LCD
SDA
SCL
SYNC
CLK
OSC
PCF85176
(2)
40 segment drives
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 V_SS
LCD PANEL
SDA
SCL
SYNC
CLK
OSC
VDD VLCD
40 segment drives
PCF85176
(1)
4 backplanes
BP0 to BP3
V_SS
A0 A1 A2 SA0 V_SS
013aaa297
(1) Is master (OSC connected to V_SS).
(2) Is slave (OSC connected to V_DD).
Fig 23. Cascaded PCF85176 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85176. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex drive mode when PCF85176
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF85176 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF85176 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF85176 are shown in Figure 24.
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 19.
PCF85176_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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