P89LPC9331 Datasheet, PDF (32/93 Pages) NXP Semiconductors – 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
XTAL1
XTAL2
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
RTC
ADC1
ADC0
RC OSCILLATOR
RCCLK
WITH CLOCK DOUBLER
(7.3728 MHz/14.7456 MHz ± 1 %)
WATCHDOG
OSCILLATOR
(400 kHz ± 5 %)
TIMER 0 AND
TIMER 1
OSCCLK
CCLK
DIVM
÷2
PCLK
PCLK
I²C-BUS
SPI
UART
Fig 7. Block diagram of oscillator control
CPU
WDT
32 × PLL
CCU
(P89LPC9351/9361)
002aad559
7.10 CCLK wake-up delay
The P89LPC9331/9341/9351/9361 has an internal wake-up timer that delays the clock
until it stabilizes depending on the clock source used. If the clock source is any of the
three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK
cycles plus 60 µs to 100 µs. If the clock source is the internal RC oscillator, the delay is
200 µs to 300 µs. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC9331/9341/9351/9361 is designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1
to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz or
slower.
P89LPC9331_9341_9351_9361_3
Product data sheet
Rev. 03 — 2 June 2009
© NXP B.V. 2009. All rights reserved.
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