LPC2361_10 Datasheet, PDF (32/57 Pages) NXP Semiconductors – Single-chip 16-bit/32-bit MCU; up to 128 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC

NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
7.24.6 Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM or the SRAM. This allows code running in different memory spaces to have control
of the interrupts.
7.25 Emulation and debugging
The LPC2361/2362 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
7.25.1 EmbeddedICE
The EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.
The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program flow or even entering the debug state. The
DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S
core. The DCC allows the JTAG port to be used for sending and receiving data without
affecting the normal program flow. The DCC data and control registers are mapped in to
addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than ¹â„₆ of the CPU clock (CCLK) for the JTAG
interface to operate.
7.25.2 Embedded trace
Since the LPC2361/2362 have significant amounts of on-chip memories, it is not possible
to determine how the processor core is operating simply by observing the external pins.
The ETM provides real-time trace capability for deeply embedded processor cores. It
outputs information about processor execution to a trace port. A software debugger allows
configuration of the ETM using a JTAG interface and displays the trace information that
has been captured.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
Trace Port Analyzer captures the trace information under software debugger control. The
trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)
shows the flow of execution of the processor and provides a list of all the instructions that
were executed. Instruction trace is significantly compressed by only broadcasting branch
addresses as well as a set of status signals that indicate the pipeline status on a cycle by
cycle basis. Trace information generation can be controlled by selecting the trigger
resource. Trigger resources include address comparators, counters and sequencers.
LPC2361_62_4
Product data sheet
Rev. 04 — 4 March 2010
© NXP B.V. 2010. All rights reserved.
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