PCF8531_1008 Datasheet, PDF (31/51 Pages) NXP Semiconductors – 34 x 128 pixel matrix driver

NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
slave address
S 0 1 1 1 1 0 SA0 R/W A
Fig 18. Slave address and control byte
control byte
Co RS X X X X X X
mgs474
acknowledge
from PCF8531
acknowledge
from PCF8531
acknowledge
from PCF8531
acknowledge
from PCF8531
acknowledge
from PCF8531
S
S 0 1 1 1 1 0 A 0 A 1 RS control byte A
0
data byte
slave address
R/W Co
2n ≥ 0 bytes
Fig 19. Master transmits to slave receiver; write mode
A 0 RS control byte A
data byte
AP
1 byte
Co
n ≥ 0 bytes
MSB . . . . . . . . . . . LSB
mgs475
10.3 Command decoder
The command decoder identifies command words that arrive on the I²C-bus. The most
significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates
that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it
indicates that a series of data bytes (either command or RAM data) may follow. The DB6
bit of a control byte is the RAM data/command bit RS. When this bit is logic 1, it indicates
that another RAM data byte will be transferred next. If the bit is logic 0, it indicates that
another command byte will be transferred next.
• Pairs of bytes; information in the second byte, the first byte determines whether
information is display or instruction data
• Stream of information bytes after Co = 0; display or instruction data, depending on last
RS.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 10 August 2010
© NXP B.V. 2010. All rights reserved.
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