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| PCAL9554B Datasheet, PDF (31/42 Pages) NXP Semiconductors – Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O | |||
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NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
DUT
a. P port load configuration
SCL
P0
Pn
500 Ω
CL = 50 pF 500 Ω
2 Ã VDD
002aag805
0.7 Ã VDD
A
P7
0.3 Ã VDD
SDA
tv(Q)
Pn
b. Write mode (R/W = 0)
unstable
data
last stable bit
002aag806
SCL
P0
A
P7
tsu(D)
th(D)
0.7 Ã VDD
0.3 Ã VDD
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 ï´ VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ï£ 10 MHz; Zo = 50 ï; tr/tf ï£ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 31. P port load circuit and voltage waveforms
PCAL9554B_PCAL9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 â 10 December 2012
© NXP B.V. 2012. All rights reserved.
31 of 42
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