PCA9541A Datasheet, PDF (30/41 Pages) NXP Semiconductors – 2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors
PCA9541A
2-to-1 I²C-bus master selector with interrupt logic and reset
13. Dynamic characteristics
Table 17. Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode Fast-mode I²C-bus Unit
I²C-bus
Min Max
Min
Max
t_PD
propagation delay
(SDA_MSTn to ^[1] -
0.3
SDA_SLAVE) or
(SCL_MSTn to
SCL_SLAVE)
-
0.3 ns
f_SCL
f_{SCL(init/rec)}
SCL clock frequency
SCL clock frequency
(bus initialization/bus recovery)
0
100
50
150
0
400 kHz
50
150 kHz
t_BUF
bus free time between a STOP and
START condition
4.7
-
1.3
- µs
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
[2] _4.0
-
4.7
-
4.0
-
4.7
-
0.6
- µs
1.3
- µs
0.6
- µs
0.6
- µs
t_SU;STO
t_HD;DAT
t_SU;DAT
t_r
t_f
C_b
t_SP
set-up time for STOP condition
data hold time
data set-up time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
pulse width of spikes that must be
suppressed by the input filter
4.0
-
0.6
- µs
0^[3]
3.45
0^[3]
0.9 µs
250
-
100
- ns
-
1000 20 + 0.1C_b[4] 300 ns
-
300 20 + 0.1C_b[4] 300 ns
-
400
-
400 pF
-
50
-
50 ns
t_VD;DAT
data valid time
HIGH-to-LOW
[5]
-
1
LOW-to-HIGH
[5]
-
0.6
-
1 µs
-
0.6 µs
t_VD;ACK
INT
data valid acknowledge time
-
1
-
1 µs
t_{v(INT_IN-INTn)} valid time from pin INT_IN to pin INTn
signal
-
4
-
4 µs
t_{d(INT_IN-INTn)} delay time from pin INT_IN to pin INTn
inactive
-
2
-
2 µs
t_w(rej)L
t_w(rej)H
RESET
LOW-level rejection time
HIGH-level rejection time
INT_IN input
INT_IN input
1
-
0.5
-
1
- µs
0.5
- µs
t_w(rst)L
t_rst
t_REC;STA
LOW-level reset time
reset time
recovery time to START condition
SDA clear
10
-
500
-
[6][7]
0
-
10
- ns
500
- ns
0
- ns
[1] Pass gate propagation delay is calculated from the 20 Ω typical R_on and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
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