ADC1113S125 Datasheet, PDF (30/38 Pages) NXP Semiconductors – Single 11-bit ADC; serial JESD204A interface

NXP Semiconductors
ADC1113S125
Single 11-bit ADC; serial JESD204A interface
Table 34. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit Symbol
Access
7 to 4 -
-
3 to 0 BID[3:0]
R/W
Value
0000
1010
Description
not used
defines the bank ID – extension to DID
Table 35. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit Symbol
Access Value
7
SCR
R/W
0
6 to 1 -
-
000000
0
L
R/W
0
Description
scrambling enabled
not used
defines the number of lanes per converter device, minus 1
Table 36. Cfg_4_F (address 0823h)
Default values are highlighted.
Bit Symbol
Access
7 to 3 -
-
2 to 0 F[2:0]
R/W
Value
00000
***
Description
not used
defines the number of octets per frame, minus 1
Table 37. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit Symbol
Access
7 to 5 -
-
4 to 0 K[4:0]
R/W
Value
000
*****
Description
not used
defines the number of frames per multiframe, minus 1
Table 38. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit Symbol
Access
7 to 1 -
-
0
M
R/W
Value
0000000
*
Description
not used
defines the number of converters per device, minus 1
Table 39. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit Symbol
Access
7
-
-
6
CS[0]
R/W
5 to 4 -
-
3 to 0 N[3:0]
R/W
Value
0
1
00
0001
Description
not used
defines the number of control bits per sample, minus 1
not used
defines the converter resolution
Table 40. Cfg_8_Np (address 0827h)
Default values are highlighted.
Bit Symbol
Access
7 to 5 -
-
4 to 0 NP[4:0]
R/W
Value
000
01111
Description
not used
defines the total number of bits per sample, minus 1
ADC1113S125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 March 2011
© NXP B.V. 2011. All rights reserved.
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