SC68C2550B Datasheet, PDF (3/36 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode mP interface

NXP Semiconductors
4. Block diagram
SC68C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC68C2550B
D0 to D7
R/W
RESET
DATA BUS
AND
CONTROL
LOGIC
TRANSMIT
FIFO
REGISTER
TRANSMIT
SHIFT
REGISTER
TXA, TXB
A0 to A3
CS
REGISTER
SELECT
LOGIC
IRQ
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
Fig 1. Block diagram of SC68C2550B
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
XTAL1 XTAL2
002aab334
SC68C2550B_3
Product data sheet
Rev. 03 — 9 October 2009
© NXP B.V. 2009. All rights reserved.
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