74HCT10D.653 Datasheet, PDF (3/5 Pages) NXP Semiconductors – Triple 3-input NAND gate

Philips Semiconductors
Triple 3-input NAND gate
PIN DESCRIPTION
PIN NO.
1, 3, 9
2, 4, 10
13, 5, 11
12, 6, 8
7
14
SYMBOL
1A to 3A
1B to 3B
1C to 3C
1Y to 3Y
GND
V_CC
NAME AND FUNCTION
data inputs
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
Product specification
74HC/HCT10
Fig.1 Pin configuration.
Fig.4 Functional diagram.
December 1990
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.5 Logic diagram (one gate).
FUNCTION TABLE
INPUTS
nA nB nC
L
L
L
L
L
H
L
H
L
L
H
H
OUTPUT
nY
H
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
HHH
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
3