74HC138D-Q100 Datasheet, PDF (3/18 Pages) NXP Semiconductors – 3-to-8 line decoder/demultiplexer; inverting

NXP Semiconductors
74HC138-Q100; 74HCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
A2
A1
A0
E1
E2
E3
Fig 3. Logic diagram
5. Pinning information
5.1 Pinning
74HC138/Q100
74HCT138/Q100
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
Y7 7
GND 8
16 V_CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
aaa-003153
Fig 4. Pin configuration SO16 and TSSOP16
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
001aae059
74HC138/Q100
74HCT138/Q100
terminal 1
index area
A1 2
A2 3
E1 4
E2 5
E3 6
Y7 7
GND⁽¹⁾
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
aaa-003154
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 5. Pin configuration DHVQFN16
74HC_HCT138_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 July 2012
© NXP B.V. 2012. All rights reserved.
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