74AUP2G86 Datasheet, PDF (3/17 Pages) NXP Semiconductors – Low-power dual 2-input EXCLUSIVE-OR gate

NXP Semiconductors
6. Pinning information
6.1 Pinning
74AUP2G86
1A 1
1B 2
2Y 3
GND 4
8 V_CC
7 1Y
6 2B
5 2A
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Fig 4. Pin configuration SOT765-1 (VSSOP8)
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
74AUP2G86
1A 1
8 V_CC
1B 2
7 1Y
2Y 3
6 2B
GND 4
5 2A
001aaf174
Transparent top view
Fig 5. Pin configuration SOT833-1 (XSON8)
74AUP2G86
1A 1
1B 2
8 V_CC
7 1Y
2Y 3
6 2B
GND 4
5 2A
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Transparent top view
Fig 6. Pin configuration SOT996-2 (XSON8U)
terminal 1
index area
74AUP2G86
1Y 1
7 1A
2B 2
6 1B
2A 3
5 2Y
001aaf175
Transparent top view
Fig 7. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
V_CC
Pin description
Pin
SOT765-1, SOT833-1 and SOT996-2 SOT902-1
1, 5
7, 3
2, 6
6, 2
4
4
7, 3
1, 5
8
8
Description
data input
data input
ground (0 V)
data output
supply voltage
74AUP2G86_4
Product data sheet
Rev. 04 — 29 June 2009
© NXP B.V. 2009. All rights reserved.
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