74AUP2G80 Datasheet, PDF (3/18 Pages) NXP Semiconductors – Low-power dual D-type flip-flop; positive-edge trigger

NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
6. Pinning information
6.1 Pinning
74AUP2G80
1CP 1
1D 2
2Q 3
GND 4
Fig 4. Pin configuration SOT765-1 (VSSOP8)
8 V_CC
7 1Q
6 2D
5 2CP
001aaf308
74AUP2G80
1CP 1
8 V_CC
1D 2
7 1Q
2Q 3
6 2D
GND 4
5 2CP
001aaf309
Transparent top view
Fig 5. Pin configuration SOT833-1 (XSON8)
6.2 Pin description
Table 3.
Symbol
1CP
1D
2Q
GND
2CP
2D
1Q
V_CC
Pin description
Pin
SOT765-1/SOT833-1
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
terminal 1
index area
74AUP2G80
1Q 1
7 1CP
2D 2
6 1D
2CP 3
5 2Q
001aaf310
Transparent top view
Fig 6. Pin configuration SOT902-1 (XQFN8)
Description
clock pulse input
data input
data output
ground (0 V)
clock pulse input
data input
data output
supply voltage
74AUP2G80_2
Product data sheet
Rev. 02 — 1 August 2007
© NXP B.V. 2007. All rights reserved.
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