74AUP2G125_10 Datasheet, PDF (3/24 Pages) NXP Semiconductors – Low-power dual buffer/line driver; 3-state

NXP Semiconductors
74AUP2G125
Low-power dual buffer/line driver; 3-state
nA
nOE
Fig 3. Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74AUP2G125
1OE 1
1A 2
2Y 3
GND 4
8 V_CC
7 2OE
6 1Y
5 2A
001aae973
Fig 4. Pin configuration SOT765-1
74AUP2G125
1OE 1
1A 2
8 V_CC
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aaj471
Transparent top view
Fig 6. Pin configuration SOT996-2
nY
mna227
74AUP2G125
1OE 1
8 V_CC
1A 2
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aae974
Transparent top view
Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
terminal 1
index area
74AUP2G125
2OE 1
7 1OE
1Y 2
6 1A
2A 3
5 2Y
001aae975
Transparent top view
Fig 7. Pin configuration SOT902-1
74AUP2G125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 21 September 2010
© NXP B.V. 2010. All rights reserved.
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