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| 74AUP2G125 Datasheet, PDF (3/21 Pages) NXP Semiconductors – Low-power dual buffer/line driver; 3-state | |||
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NXP Semiconductors
74AUP2G125
Low-power dual buffer/line driver; 3-state
nA
nOE
Fig 3. Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74AUP2G125
1OE 1
1A 2
2Y 3
GND 4
8 VCC
7 2OE
6 1Y
5 2A
001aae973
Fig 4. Pin conï¬guration SOT765-1 (VSSOP8)
74AUP2G125
1OE 1
1A 2
8 VCC
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aaj471
Transparent top view
Fig 6. Pin conï¬guration SOT996-2 (XSON8U)
nY
mna227
74AUP2G125
1OE 1
8 VCC
1A 2
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aae974
Transparent top view
Fig 5. Pin conï¬guration SOT833-1 and SOT1089
(XSON8)
terminal 1
index area
74AUP2G125
2OE 1
7 1OE
1Y 2
6 1A
2A 3
5 2Y
001aae975
Transparent top view
Fig 7. Pin conï¬guration SOT902-1 (XQFN8U)
74AUP2G125_6
Product data sheet
Rev. 06 â 27 November 2009
© NXP B.V. 2009. All rights reserved.
3 of 21
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