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| 74AUP1G157_06 Datasheet, PDF (3/16 Pages) NXP Semiconductors – Low-power 2-input multiplexer | |||
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NXP Semiconductors
74AUP1G157
Low-power 2-input multiplexer
S
I1
I0
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
Y
001aac654
74AUP1G157
I1 1
6S
GND 2
5 VCC
I0 3
4Y
001aae015
Fig 5. Pin conï¬guration SOT363
(SC-88)
74AUP1G157
I1 1
6S
GND 2
5 VCC
I0 3
4Y
001aae016
Transparent top view
Fig 6. Pin conï¬guration SOT886
(XSON6)
6.2 Pin description
Table 3.
Symbol
I1
GND
I0
Y
VCC
S
Pin description
Pin
1
2
3
4
5
6
Description
data input from source 1
ground (0 V)
data input from source 0
multiplexer output
supply voltage
common data select input
74AUP1G157
I1 1
6S
GND 2
5 VCC
I0 3
4Y
001aae017
Transparent top view
Fig 7. Pin conï¬guration SOT891
(XSON6)
74AUP1G157_1
Product data sheet
Rev. 01 â 9 November 2006
© NXP B.V. 2006. All rights reserved.
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