PCA9622_12 Datasheet, PDF (28/39 Pages) NXP Semiconductors – 16-bit Fm+ I2C-bus 100 mA 40 V LED driver

NXP Semiconductors
PCA9622
16-bit Fm+ I²C-bus 100 mA 40 V LED driver
14. Dynamic characteristics
Table 17. Dynamic characteristics
Symbol Parameter
Conditions
Standard-mode Fast-mode I²C-bus Fast-mode Unit
I²C-bus
Plus I²C-bus
Min Max
Min
Max Min Max
f_SCL
SCL clock frequency
t_BUF
bus free time between
a STOP and START
condition
0
100
4.7
-
0
400 0 1000 kHz
1.3
- 0.5
- s
t_HD;STA hold time (repeated)
START condition
4.0
-
0.6
- 0.26 - s
t_SU;STA
set-up time for a
repeated START
condition
4.7
-
0.6
- 0.26 - s
t_SU;STO set-up time for STOP
condition
4.0
-
0.6
- 0.26 - s
t_HD;DAT
t_VD;ACK
data hold time
data valid acknowledge
time
0
[1] _0.3
-
3.45
0
-
0
- ns
0.1
0.9 0.05 0.45 s
t_VD;DAT
t_SU;DAT
t_LOW
data valid time
data set-up time
LOW period of the SCL
clock
[2] _0.3
250
4.7
3.45
-
-
0.1
0.9 0.05 0.45 s
100
-
50
- ns
1.3
- 0.5
- s
t_HIGH
HIGH period of the
SCL clock
4.0
-
0.6
- 0.26 - s
t_f
fall time of both SDA
and SCL signals
[3][4]
-
300 20 + 0.1C_b[5] 300
-
120 ns
t_r
rise time of both SDA
and SCL signals
-
1000 20 + 0.1C_b[5] 300
-
120 ns
t_SP
pulse width of spikes
that must be
suppressed by the
input filter
[6]
-
50
-
50
-
50 ns
Output propagation delay
t_PLH
LOW to HIGH
propagation delay
OE to LEDn;
MODE2[1:0] = 01
-
-
-
-
-
150 ns
t_PHL
HIGH to LOW
propagation delay
OE to LEDn;
MODE2[1:0] = 01
-
-
-
-
-
150 ns
Output port timing
t_d(SCL-Q) delay time from SCL
to data output
SCL to LEDn;
MODE2[3] = 1;
outputs change on
ACK
-
-
-
-
-
450 ns
t_d(SDA-Q) delay time from SDA
to data output
SDA to LEDn;
MODE2[3] = 0;
outputs change on
STOP condition
-
-
-
-
-
450 ns
[1] t_VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
PCA9622
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 September 2012
© NXP B.V. 2012. All rights reserved.
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