74AUP1T45 Datasheet, PDF (27/33 Pages) NXP Semiconductors – Low-power dual supply translating transceiver; 3-state

NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
13.3 Power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply
current, bus contention, oscillations, or other anomalies. Take the following precautions to
guard against such power-up problems:
• Connect ground before any supply voltage is applied.
• Power-up V_CC(A).
• V_CC(B) can be ramped up along with or after V_CC(A).
13.4 Enable times
Calculate the enable times for the 74AUP1T45 using the following formulas:
• t_PZH (DIR to A) = t_PLZ (DIR to B) + t_PLH (B to A)
• t_PZL (DIR to A) = t_PHZ (DIR to B) + t_PHL (B to A)
• t_PZH (DIR to B) = t_PLZ (DIR to A) + t_PLH (A to B)
• t_PZL (DIR to B) = t_PHZ (DIR to A) + t_PHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time
the DIR bit is switched until an output is expected. For example, if the 74AUP1T45 initially
is transmitting from A to B, then the DIR bit is switched, the B port of the device must be
disabled before presenting it with an input. After the B port has been disabled, an input
signal applied to it appears on the corresponding A port after the specified propagation
delay.
74AUP1T45_2
Product data sheet
Rev. 02 — 3 August 2009
© NXP B.V. 2009. All rights reserved.
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