SC16C850 Datasheet, PDF (26/53 Pages) NXP Semiconductors – 2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface

NXP Semiconductors
SC16C850
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Table 12.
FCR[5]
0
0
1
1
TX FIFO trigger levels
FCR[4]
TX FIFO trigger level (bytes) in 32-byte FIFO mode^[1]
0
16
1
8
0
24
1
30
[1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).
7.4 Interrupt Status Register (ISR)
The SC16C850 provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 13 “Interrupt source” shows the
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 13. Interrupt source
Priority ISR[5] ISR[4] ISR[3]
level
1
0
0
0
2
0
0
0
2
0
0
1
3
0
0
0
4
0
0
0
5
0
1
0
6
1
0
0
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
ISR[0]
0
0
0
0
0
0
0
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/
Special character
CTS, RTS change of state
Table 14. Interrupt Status Register bits description
Bit Symbol Description
7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C850 mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see Table 13).
logic 0 or cleared = default condition
SC16C850_1
Product data sheet
Rev. 01 — 10 January 2008
© NXP B.V. 2008. All rights reserved.
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