SC16C850L Datasheet, PDF (25/54 Pages) NXP Semiconductors – 1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface

NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO
trigger levels.
7.3.1 FIFO mode
Table 10. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode^[1].
These bits are used to set the trigger levels for receive FIFO interrupt and flow
control. The SC16C850L will issue a receive ready interrupt when the number
of characters in the receive FIFO reaches the selected trigger level. Refer to
Table 11.
5:4 FCR[5:4] Transmit trigger level in 32-byte FIFO mode^[2].
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850L will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 12.
3
FCR[3] reserved
2
FCR[2] XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1] RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0] FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
[1] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.
[2] For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.
Table 11.
FCR[7]
0
0
1
1
RCVR trigger levels
FCR[6]
RX FIFO trigger level (bytes) in 32-byte FIFO mode^[1]
0
8
1
16
0
24
1
28
[1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).
SC16C850L_4
Product data sheet
Rev. 04 — 13 December 2007
© NXP B.V. 2007. All rights reserved.
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