SC16C752B Datasheet, PDF (25/47 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

NXP Semiconductors
SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.6 Modem Control Register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem. Table 14 shows modem control register bit settings.
Table 14. Modem Control Register bits description
Bit Symbol Description
7
MCR[7]^[1] Clock select.
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6
MCR[6]^[1] TCR and TLR enable.
logic 0 = no action
logic 1 = enable access to the TCR and TLR registers
5
MCR[5]^[1] Xon Any.
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
4
MCR[4] Enable loopback.
logic 0 = normal operating mode.
logic 1 = enable local Loopback mode (internal). In this mode the MCR[3:0]
signals are looped back into MSR[7:4] and the TX output is looped back to
the RX input internally.
3
MCR[3] IRQ enable OP.
logic 0 = forces INTA, INTB outputs to the 3-state mode and OP output to
HIGH state
logic 1 = forces the INTA-INTB outputs to the active state and OP output to
LOW state. In Loopback mode, controls MSR[7].
2
MCR[2] FIFO Ready enable.
logic 0 = disable the FIFO Rdy register
logic 1 = enable the FIFO Rdy register. In Loopback mode, controls MSR[6].
1
MCR[1] RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 =force RTS output to active (LOW). In loopback mode, controls
MSR[4]. If auto-RTS is enabled, the RTS output is controlled by hardware
flow control.
0
MCR[0] DTR
logic 0 = force DTR output to inactive (HIGH)
logic 1 = force DTR output to active (LOW). In Loopback mode, controls
MSR[5].
[1] MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable.
SC16C752B_5
Product data sheet
Rev. 05 — 2 October 2008
© NXP B.V. 2008. All rights reserved.
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