LPC2939 Datasheet, PDF (25/99 Pages) NXP Semiconductors – ARM9 microcontroller with CAN, LIN, and USB

NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
6.8.5 Clock description
The flash memory controller is clocked by CLK_SYS_FMC, see Section 6.7.2.
6.8.6 EEPROM
EEPROM is a non-volatile memory mostly used for storing relatively small amounts of
data, for example for storing settings. It contains one 16 kB memory block and is
byte-programmable and byte-erasable.
The EEPROM can be accessed only through the flash controller.
6.9 External Static Memory Controller (SMC)
The LPC2939 contains an external Static Memory Controller (SMC) which provides an
interface for external (off-chip) memory devices.
Key features are:
• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices
• Asynchronous page-mode read operation in non-clocked memory subsystems
• Asynchronous burst-mode read access to burst-mode ROM devices
• Independent configuration for up to eight banks, each up to 16 MB
• Programmable bus-turnaround (idle) cycles (one to 16)
• Programmable read and write wait states (up to 32), for static RAM devices
• Programmable initial and subsequent burst-read wait state for burst-ROM devices
• Programmable write protection
• Programmable burst-mode operation
• Programmable external data width: 8 bit, 16 bit, or 32 bit
• Programmable read-byte lane enable control
6.9.1 Description
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory, or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory bank selection is controlled by memory
addressing. Table 11 shows how the 32-bit system address is mapped to the external bus
memory base addresses, chip selects, and bank internal addresses.
LPC2939_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 7 April 2010
© NXP B.V. 2010. All rights reserved.
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