ADC1015S Datasheet, PDF (24/39 Pages) NXP Semiconductors – Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Preliminary data sheet

NXP Semiconductors
ADC1015S series
ADC1015S series; input buffer; CMOS or LVDS DDR digital output
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see Table 23).
3.5 mA
typ
VCCO
−
+
D_nP/D_{n + 1}P
D_nM/D_{n + 1}M
100 Ω RECEIVER
+
−
OGND
005aaa058
Fig 20. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 20) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 21 and
Table 32).
3.5 mA
typ
VCCO
−
+
D_xP/D_{x + 1}P
100 Ω
D_xM/D_{x + 1}M
RECEIVER
+
−
OGND
005aaa059
Fig 21. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
Table 13. LVDS DDR output register 2
LVDS_INT_TER[2:0]
000
001
010
011
100
Resistor value (Ω)
no internal termination
300
180
110
150
ADC1015S_SER_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
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