PCAL9555A Datasheet, PDF(23/46 Page) NXP Semiconductors – Low-voltage 16-bit I2C-bus GPIO with Agile I/O, interrupt and weak pull-up

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PCAL9555A Datasheet, PDF (23/46 Pages) NXP Semiconductors – Low-voltage 16-bit I2C-bus GPIO with Agile I/O, interrupt and weak pull-up

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NXP Semiconductors

PCAL9555A

Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up

Table 28. Recommended supply sequencing and ramp rates

Tamb = 25 ï°C (unless otherwise noted). Not tested; specified by design.

Symbol Parameter

Condition

Min Typ Max Unit

(dV/dt)f fall rate of change of voltage

Figure 17

0.1

(dV/dt)r rise rate of change of voltage

Figure 17

0.1

td(rst)

reset delay time

Figure 17; re-ramp time when

VDD drops below 0.2 V or to VSS

Figure 18; re-ramp time when

VDD drops to VPOR(min) ï 50 mV

ïVDD(gl) glitch supply voltage difference

Figure 19

[1] -

tw(gl)VDD supply voltage glitch pulse width Figure 19

[2] -

VPOR(trip) power-on reset trip voltage

falling VDD

0.7

rising VDD

2000 ms

ïs

1.4

[1] Level that VDD can glitch down to with a ramp rate of 0.4 ïs/V, but not cause a functional disruption when tw(gl)VDD < 1 ïs.

[2] Glitch width that will not cause a functional disruption when ïVDD(gl) = 0.5 ï´ VDD.

Glitches in the power supply can also affect the power-on reset performance of this

device. The glitch width (tw(gl)VDD) and glitch height (ïVDD(gl)) are dependent on each

other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 19 and Table 28 provide more information on

how to measure these specifications.

VDD

âVDD(gl)

tw(gl)VDD

time

002aah331

Fig 19. Glitch width and glitch height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition

is released and all the registers and the I2C-bus/SMBus state machine are initialized to

their default states. The value of VPOR differs based on the VDD being lowered to or from

0 V. Figure 20 and Table 28 provide more details on this specification.

VDD

VPOR (rising VDD)

VPOR (falling VDD)

time

POR

PCAL9555A

Product data sheet

Fig 20. Power-on reset voltage (VPOR)

All information provided in this document is subject to legal disclaimers.

Rev. 1 â 3 October 2012

time

002aah332

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