LPC2420_10 Datasheet, PDF (23/79 Pages) NXP Semiconductors – Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface

NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
Table 4. Pin description …continued
Symbol
Pin
Ball
P4[25]/WE
179^[1] B9^[1]
P4[26]/BLS0
119^[1] L15^[1]
P4[27]/BLS1
139^[1] G15^[1]
P4[28]/BLS2/
MAT2[0]/TXD3
170^[1] C11^[1]
P4[29]/BLS3/
MAT2[1]/RXD3
176^[1] B10^[1]
P4[30]/CS0
P4[31]/CS1
ALARM
USB_D−2
DBGEN
TDO
TDI
TMS
TRST
TCK
RTCK
RSTOUT
RESET
XTAL1
XTAL2
RTCX1
RTCX2
187^[1] B7^[1]
193^[1] A4^[1]
37^[8]
N1^[8]
52
U1
9^[1]
F4^[1]
2^[1]
4^[1]
6^[1]
8^[1]
10^[1]
D3^[1]
C2^[1]
E3^[1]
D1^[1]
E2^[1]
206^[1] C3^[1]
29
35^[7]
K3
M2^[7]
44^[8]
46^[8]
34^[8]
36^[8]
M4^[8]
N4^[8]
K2^[8]
L2^[8]
Type
I/O
O
I/O
O
I/O
O
I/O
O
O
O
I/O
O
O
I
I/O
O
I/O
O
O
I/O
I
O
I
I
I
I
I/O
O
I
I
O
I
O
Description
P4[25] — General purpose digital input/output pin.
WE — LOW active Write Enable signal.
P4[26] — General purpose digital input/output pin.
BLS0 — LOW active Byte Lane select signal 0.
P4[27] — General purpose digital input/output pin.
BLS1 — LOW active Byte Lane select signal 1.
P4 [28] — General purpose digital input/output pin.
BLS2 — LOW active Byte Lane select signal 2.
MAT2[0] — Match output for Timer 2, channel 0.
TXD3 — Transmitter output for UART3.
P4[29] — General purpose digital input/output pin.
BLS3 — LOW active Byte Lane select signal 3.
MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.
P4[30] — General purpose digital input/output pin.
CS0 — LOW active Chip Select 0 signal.
P4[31] — General purpose digital input/output pin.
CS1 — LOW active Chip Select 1 signal.
ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when
a RTC alarm is generated.
USB_D−2 — USB port 2 bidirectional D− line.
DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO — Test data out for JTAG interface.
TDI — Test data in for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be slower than ¹â„₆
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2420/2460
being in Reset state.
external reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
LPC2420_60_5
Preliminary data sheet
Rev. 05 — 24 February 2010
© NXP B.V. 2010. All rights reserved.
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