LPC1102 Datasheet, PDF (23/38 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

NXP Semiconductors
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Conditions: V_DD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System PLL disabled; IRC enabled.
(2) System PLL enabled; IRC disabled.
Fig 8. Sleep mode: Typical supply current I_DDversus temperature for different system
clock frequencies
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Fig 9.
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Deep-sleep mode: Typical supply current I_DD versus temperature for different
supply voltages V_DD
LPC1102
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00 — 23 June 2010
© NXP B.V. 2010. All rights reserved.
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