ADC1410S Datasheet, PDF (23/37 Pages) NXP Semiconductors – Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1410S series
ADC1410S series; CMOS or LVDS DDR digital output
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0]
000
001
010
011
100
101
110
111
Resistor value (Ω)
no internal termination
300
180
110
150
100
81
60
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1410S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1;
see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The
Fast OTR detection threshold (below full-scale) can be programmed via bits
FASTOTR_DET[2:0].
Table 15. Fast OTR register
FASTOTR_DET[2:0]
000
001
010
011
100
101
110
111
Detection level (dB)
−20.56
−16.12
−11.02
−7.82
−5.49
−3.66
−2.14
−0.86
11.5.5 Digital offset
By default, the ADC1410S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1410S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern
can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected
when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless
of the analog input.
ADC1410S_SER_3
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
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