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PCF8564A Datasheet, PDF (22/44 Pages) NXP Semiconductors – Real time clock and calendar
NXP Semiconductors
PCF8564A
Real time clock and calendar
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
Fig 14. System configuration
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
mba605
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 15.
data output
by transmitter
data output
by receiver
SCL from
master
S
1
2
START
condition
Fig 15. Acknowledgment on the I2C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
mbc602
PCF8564A_1
Product data sheet
Rev. 1 — 8 October 2009
© NXP B.V. 2009. All rights reserved.
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