PCF2129A_10 Datasheet, PDF (22/69 Pages) NXP Semiconductors – Integrated RTC, TCXO and quartz crystal

NXP Semiconductors
PCF2129A
Integrated RTC, TCXO and quartz crystal
The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic
1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in
Figure 12. All timings shown are required minimum.
power up
8 ms
SDA/CE
minimum 500 ns
minimum 2000 ns
SCL
reset override
001aaj326
Fig 12. Power-On Reset Override (PORO) sequence, valid for both I²C-bus and SPI-bus
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
PCF2129A_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 May 2010
© NXP B.V. 2010. All rights reserved.
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