SC16C754B Datasheet, PDF (21/51 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
XTAL1
XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
Fig 14. Crystal oscillator connection
XTAL1
XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
C2
47 pF
002aaa870
7. Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table 9.
Table 9.
A2 A1
00
00
01
01
10
10
11
11
00
00
01
10
10
11
11
11
11
11
Register map - read/write properties
A0 Read mode
0 Receive Holding Register (RHR)
1 Interrupt Enable Register (IER)
0 Interrupt Identification Register (IIR)
1 Line Control Register (LCR)
0 Modem Control Register (MCR)^[1]
1 Line Status Register (LSR)
0 Modem Status Register (MSR)
1 ScratchPad Register (SPR)
0 Divisor Latch LSB (DLL)^[2][3]
1 Divisor Latch MSB (DLM)^[2][3]
0 Enhanced Feature Register (EFR)^[2][4]
0 Xon1 word^[2][4]
1 Xon2 word^[2][4]
0 Xoff1 word^[2][4]
1 Xoff2 word^[2][4]
0 Transmission Control Register
(TCR)^[2][5]
1 Trigger Level Register (TLR)^[2][5]
1 FIFO ready register^[2][6]
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register (IER)
FIFO Control Register (FCR)
Line Control Register (LCR)
Modem Control Register (MCR)^[1]
not applicable
not applicable
ScratchPad Register (SPR)
Divisor Latch LSB (DLL)^[2][3]
Divisor Latch MSB (DLM)^[2][3]
Enhanced Feature Register (EFR)^[2][4]
Xon1 word^[2][4]
Xon2 word^[2][4]
Xoff1 word^[2][4]
Xoff2 word^[2][4]
Transmission Control Register
(TCR)^[2][5]
Trigger Level Register (TLR)^[2][5]
[1] MCR[7] can only be modified when EFR[4] is set.
[2] Accessed by a combination of address pins and register bits.
[3] Accessible only when LCR[7] is logic 1.
[4] Accessible only when LCR is set to 1011 1111 (BFh).
[5] Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.
[6] Accessible only when CSA to CSD = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).
SC16C754B_4
Product data sheet
Rev. 04 — 6 October 2008
© NXP B.V. 2008. All rights reserved.
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