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PCF8562_09 Datasheet, PDF (21/36 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562.
The least significant bit of the slave address that a PCF8562 will respond to is defined by
the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to
a read access.
The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF8562
slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCF8562s whose SA0 inputs are set to the alternative level.
R/W
slave address
acknowledge by
all addressed
PCF8576Ds
acknowledge
by A0, A1 and A2
selected
PCF8576D only
S
S 0 1 1 1 0 0A 0AC
0
COMMAND
A DISPLAY DATA
AP
1 byte
Fig 15. I2C-bus protocol
n ≥ 1 byte(s)
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
mdb078
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8562.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 16). The command bytes are also acknowledged by all addressed
PCF8562s on the bus.
MSB
C
LSB
REST OF OPCODE
Fig 16. Format of command byte
msa833
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically
updated.
PCF8562_4
Product data sheet
Rev. 04 — 18 March 2009
© NXP B.V. 2009. All rights reserved.
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