PCF8564A_1308 Datasheet, PDF (20/48 Pages) NXP Semiconductors – Real time clock and calendar

NXP Semiconductors
PCF8564A
Real time clock and calendar
Table 28. Register reset values^[1]
Address Register name Bit
7
6
5
4
3
2
1
0
00h
Control_1
0
0
0
0
1
0
0
0
01h
Control_2
0
0
0
0
0
0
0
0
02h
Seconds
1
x
x
x
x
x
x
x
03h
Minutes
x
x
x
x
x
x
x
x
04h
Hours
x
x
x
x
x
x
x
x
05h
Days
x
x
x
x
x
x
x
x
06h
Weekdays
x
x
x
x
x
x
x
x
07h
Months
x
x
x
x
x
x
x
x
08h
Years
x
x
x
x
x
x
x
x
09h
Minute_alarm
1
x
x
x
x
x
x
x
0Ah
Hour_alarm
1
x
x
x
x
x
x
x
0Bh
Day_alarm
1
x
x
x
x
x
x
x
0Ch
Weekday_alarm 1
x
x
x
x
x
x
x
0Dh
CLKOUT_ctrl
1
x
x
x
x
x
0
0
0Eh
Timer_ctrl
0
x
x
x
x
x
1
1
0Fh
Timer
x
x
x
x
x
x
x
x
[1] Registers marked ‘x’ are undefined at power-on and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a circuit has been implemented to
disable the POR and speed up functional test of the module. The setting of this mode
requires that the I²C signals on the pins SDA and SCL are toggled as illustrated in
Figure 10. All timings shown are required minimums.
Once the override mode has been entered, the chip immediately stops, being reset, and
normal operation may begin, i.e., entry into the EXT_CLK test mode via I²C access. The
override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1
before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal
operation has no effect, except to prevent entry into the POR override mode.
6'$
QV
QV
6&/
PV
SRZHURQ
Allow 500 ns between the edges of either signal.
Fig 10. POR override sequence
RYHUULGHDFWLYH PJP
PCF8564A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 26 August 2013
© NXP B.V. 2013. All rights reserved.
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