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PCA9673 Datasheet, PDF (20/33 Pages) NXP Semiconductors – Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
[1] The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD).
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
[3] The value is not tested, but verified on sampling basis.
13. Dynamic characteristics
Table 6. Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Standard mode Fast mode I2C-bus
I2C-bus
Min Max
Min
Max
fSCL
SCL clock frequency
tBUF
bus free time between a
STOP and START condition
0
100
4.7
-
0
400
1.3
-
tHD;STA hold time (repeated) START
condition
4.0
-
0.6
-
tSU;STA set-up time for a repeated
START condition
4.7
-
0.6
-
tSU;STO set-up time for STOP
condition
4.0
-
0.6
-
tHD;DAT
tVD;ACK
data hold time
data valid acknowledge
time [1]
0
-
0
-
0.3 3.45
0.1
0.9
tVD;DAT
tSU;DAT
tLOW
tHIGH
data valid time[2]
data set-up time
LOW period of the SCL clock
HIGH period of the SCL
clock
300
-
250
-
4.7
-
4.0
-
50
-
100
-
1.3
-
0.6
-
tf
fall time of both SDA and
SCL signals
[4][5]
-
300 20 + 0.1Cb[3] 300
tr
rise time of both SDA and
SCL signals
-
1000 20 + 0.1Cb[3] 300
tSP
pulse width of spikes that
must be suppressed by the
input filter[6]
-
50
-
50
Port timing; CL ≤ 100 pF (see Figure 16 and Figure 17)
tv(Q)
data output valid time
-
4
tsu(D)
data input set-up time
0
-
th(D)
data input hold time
4
-
Interrupt timing; CL ≤ 100 pF (see Figure 16 and Figure 17)
tv(D)
data input valid time
-
4
td(rst)
reset delay time
-
4
Reset timing (see Figure 27)
-
4
0
-
4
-
-
4
-
4
tw(rst)
trec(rst)
trst
reset pulse width
reset recovery time
reset time
4
-
0
-
100
-
4
-
0
-
100
-
Fast-mode Unit
Plus I2C-bus
Min Max
0 1000 kHz
0.5
- µs
0.26
- µs
0.26
- µs
0.26
- µs
0
- ns
0.05 0.45 µs
50 450 ns
50
- ns
0.5
- µs
0.26
- µs
-
120 ns
-
120 ns
-
50 ns
-
4 µs
0
- µs
4
- µs
-
4 µs
-
4 µs
4
- ns
0
- ns
100
- ns
PCA9673_1
Product data sheet
Rev. 01 — 1 February 2007
© NXP B.V. 2007. All rights reserved.
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